Aplus Announces Support for Xilinx's Virtex-II Device Family

LOS ANGELES--(BUSINESS WIRE)--Dec. 16, 2002--Aplus Design Technologies, Inc., the leader of automated physical synthesis solution for programmable logic devices, today announced the support of Xilinx Virtex-II(TM) platform FPGA device family in its physical synthesis tool PALACE(TM) version 2.2. The support for Virtex-II device family helps Xilinx customers with a fast and simple solution to meet aggressive timing goals.

Physical And Logic Automatic Compilation Engine

Aplus' Physical And Logic Automatic Compilation Engine (PALACE) is a new generation of physical synthesis solution for programmable logic devices. PALACE features the industry's first constraint-driven optimization and mapping, automatic multi-clock retiming, and placement-driven synthesis. Unifying synthesis and placement eliminates the need of lengthy iterations between logic and physical designs. The result is significant circuit performance improvement without user manual interventions, floorplanning, or re-synthesis.

Extensive benchmarking shows that PALACE 2.2, coupled with Xilinx's ISE Alliance implementation tools, boosts performance by one speed-grade or higher for a wide range of designs when compared to the best available FPGA synthesis flow. PALACE further enhances design productivity and shortens design cycle by reducing the number of iterations.

"It is crucially important to accelerate timing closure and design productivity of advanced multimillion-gate Virtex-II designs," said Rajeev Jayaraman, director of FPGA implementation tools at Xilinx. "To keep aggressive FPGA designs on schedule, designers have begun to use physical synthesis technologies such as PALACE in combination with Xilinx ISE Alliance implementation tools to achieve higher and more predictable performance. The fully automated physical synthesis flow by PALACE is very appealing."

"We worked closely with Xilinx to develop a highly optimized physical synthesis solution with detailed architecture modeling for Virtex-II," said Behrooz Zahiri, vice president of marketing at Aplus Design Technologies. "Built on top of Xilinx design framework, PALACE can easily be integrated with any existing Virtex-II FPGA synthesis flow to provide significant performance gain."

Pricing and Availability

PALACE 2.2 physical synthesis software is available now. Pricing for the PALACE physical synthesis software starts at $15,000 (U.S.). PALACE 2.2 may be requested by email at info@aplus-dt.com. Additional information about PALACE can be found on the World Wide Web at www.aplus-dt.com.

About Aplus Design Technologies

Aplus Design Technologies, Inc. (Aplus) is a privately held company providing advanced physical synthesis and architecture development tools for programmable logic devices. Combining advanced logic synthesis with physical design, Aplus' physical synthesis tool PALACE(TM) performs architecture specific optimization to offer at least one technology generation performance advantage over the existing design tools. The company is located in Los Angeles, and its Web site is http://www.aplus-dt.com

CONTACT: Aplus Design Technologies
	            Behrooz Zahiri, 408/528-7481
	            marketing@aplus-dt.com